Advanced Micro Devices (AMD) recently launched the Ryzen 9 7950X3D, which has received an enthusiastic response for its second-gen 3D V-Cache, despite some mixed opinions about its usefulness in a 16-core central processing unit (CPU). Now, AMD has shared some of the technical details that explain its performance.

AMD began mixing nodes in 2019 when it used the 7 nm node for the core complex die (CCD) and the 12 nm node for the input/output (IO) die of the Zen 2 microarchitecture. In its latest Zen 4 architecture, AMD has stepped up to using three nodes: the 5 nm node for the CCD, the 6 nm node for the IO die, and the 7 nm node for the V-Cache.

During its recent ISSCC presentation, AMD explained some of the challenges it faced stacking one node onto another. Both the 7950X3D and the original 5800X3D have their V-Caches positioned over their regular L3 caches to allow them to be connected. The arrangement also keeps the V-Cache away from the heat produced by the cores. However, while the V-Cache fits neatly over the L3 cache in the 5800X3D, it overlaps with the L2 caches on the edges of the cores in the 7950X3D.

One of the problems AMD faced was that it doubled the amount of L2 cache in each core from 0.5 MB in Zen 3 to 1 MB in Zen 4. However, AMD worked around the additional space constraints by punching holes through the L2 caches for the through-silicon vias (TSVs) that deliver power to the V-Cache. The signal TSVs still come from the controller in the center of the CCD, but AMD tweaked them too to reduce their footprint by 50%.

AMD shrunk the V-Cache down from 41 mm2 to 36 mm2 but maintained the same 4.7 billion transistors. Taiwan Semiconductor Manufacturing Company (TSMC) fabricates the cache on a new version of the 7 nm node that it developed especially for static random-access memory (SRAM). As a result, the V-Cache has 32% more transistors per square millimeter than the CCD, despite the CCD being manufactured on the much smaller 5 nm node.

All of the refinements and workarounds AMD implemented add up to a 25% increase in bandwidth to 2.5 terabytes per second (TB/s) and an unspecified increase in efficiency. This improvement is impressive for nine months between the first and second generations of a supplemental chiplet. The Ryzen 7 7800X3D is set to arrive in a month’s time, and it is hoped that this value will be evident in its performance as well.

The Zen 4 L2 cache is larger not only because of its larger capacity but also because it has TSVs passing through it. This allows the V-Cache to sit over the middle of the CCD, with the eight cores flanking the sides. Although the V-Cache overlaps with the L2 caches on the edges of the cores in the 7950X3D, AMD’s workarounds have made it possible for the V-Cache to function effectively.

The V-Cache’s increased transistor density has resulted in a significant increase in bandwidth. With a bandwidth of 2.5 TB/s, the Ryzen 9 7950X3D has a 25% increase in bandwidth compared to the previous generation. Additionally, the increased efficiency of the V-Cache remains unspecified but is expected to further enhance the CPU’s performance.

Despite the challenges faced by AMD in stacking one node onto another, the refinements and workarounds implemented in the Ryzen 9 7950X3D have produced impressive results. It is hoped that the value of the V-Cache will continue to be evident in future CPUs that feature this technology, such as the Ryzen 7 7800X3D, which is set to launch in the coming month. As AMD continues to push the boundaries of CPU performance, it will be exciting to see what other innovative technologies they will introduce in the future.